Source File
Analysis
π Overview
πGlobal Search
π·Tag Database0
πArrays & Registers0
β‘I/O Map0
πHardware0
Logic Intelligence
πLoop Topology0
π―Cause & Effect0
πCross Reference0
πInterlocks0
Documents
πAuto Narrative
πPID Loops0
πSequences0
π§©UDTs0
β οΈRisk Flags0
π’Compute/Calc0
π§±Add-On Instrs0
βοΈEquipment / Devices0
πStandards / Templates0
β
Engineering QA0
πRevision Diff0
Controllerβ
Programsβ
Total Tagsβ
IO Pointsβ
Rungsβ
π
CA Workbench v6
Drop an Allen-Bradley .L5X or .L5K export and explore it instantly β I/O map, tags, control loops, cause & effect, interlocks, risk flags, and auto-generated narratives. Parsed entirely in your browser.
Loads a sample controller so you can explore every panel in one click.
Global Search All entities β tags, IO, loops, C&E
π
Type to search across all program data
| Tag Name | Kind | Data Type | Scope | Address | Description |
|---|
Arrays & Register Structures
| Tag | Type | Module | Bit/Word | Description | Program |
|---|
Hardware Rack View
Loop Topology
Cause & Effect Matrix
Read each row as: this output energizes when its input conditions are satisfied. Interlocks appear as NOT/inverted conditions β see the legend.
AND condition
OR / parallel
NOT / inverted
Every tag's read/write map across all routines. Filter to catch issues: Orphan β never read or written anywhere Β· Undriven β read by logic but never written Β· Multi-write β written in more than one place (possible conflict).
Interlock Map
Safety and permissive tags β E-stops, faults, trips, bypasses β and the output coils they gate. Gates Outputs is how many outputs each one can block.
| Tag | Type | Dir | Gates Outputs | Writes | Reads | Description |
|---|
Auto-Generated Control Narrative Derived from parsed logic
PID & Analog Loops
Sequences & State Machines
User Defined Types
Risk Flags & Diagnostics
Advisory findings from the analyzer β not necessarily errors. Things worth a second look (orphaned tags, undocumented logic, unusual patterns), ranked by severity.
Program Detail
Compute & Calculation Scripts
Every computed value in the logic β CPT and math expressions with their formulas and destination tags β pulled out so the calculations are visible in one place.
Add-On Instructions
Equipment / Device Instances
Decoded from Add-On Instruction (function block) calls in ladder logic β each card is one real equipment instance (motor, valve, PID, etc.). Call arguments are mapped to their real parameter names, and the AOI's own internal interlock logic is resolved to this specific instance's wired tags. Requires AOI definitions in the export β see the Add-On Instrs panel.
Standards / Device Templates
For each device type with 2+ instances, the standard wiring is derived from how the instances are ACTUALLY wired β then instances that don't match are flagged for review. This answers "are all my pumps wired the same?" β advisory, not errors: a flagged difference may be intentional (e.g. a different process area). One-off outliers are ranked above systematic groups.
House standards library: save a type's standard as a small JSON, then check other projects against it. Your code never leaves the browser β only the tiny standard does.
Engineering QA
Automated design-review checks on the decoded equipment model β the kind of pass a senior engineer does before FAT. Advisory, not errors: a flagged item may be intentional. Findings are ranked by severity; a clean pass is a real result (e.g. "nothing left in simulation"). Tell us if a finding is useful or intentional β that feedback sharpens the checks. Runs entirely in your browser.
Revision Diff
Compare the loaded file (Rev A) against a second export (Rev B) β what actually changed at the equipment level: devices added / removed / rewired / retyped, tags added / removed. Safety-relevant wiring changes (interlock, reset, alarm) are flagged. No more scrolling two Studio 5000 windows side by side. Both files are compared entirely in your browser.
Detail & Export
π
Load a file to see detail here